Low stand-by power complementary field effect circuitry



Dec. 5; 1967 F. M. WANLASS 3,356,858

LOW STAND-BY POWER COMPLEMENTARY FIELD EFFECT CIRCUITRY Filed June 18,1963 5 sheets sheet 1 SOURCE INVENTOR.

FRANK M.WANLASS AT TO R N EYS Dec. 5, 1967 F. M. WANLASS 3,356,853

LOW STAND'BY POWER COMPLEMENTARY FIELD EFFECT CIRCUITRY Filed June 18,1965 5 Sheet-Sheet 2 SOURCE DRAIN I GATE SOURCE 4 36 ""36 4| ",4| 37-3"[' [4 P P N 35 32 33 F E-:A

. INVENTOR.

FRANK M.WANLASS ATTORNEYS -Dec.5,1967 F.M.WANLASS 3,356,858

LOW STAND-BY POWER COMPLEMENTARY FIELD EFFECT CIRCUITRY Filed June 18,1966 5 Sheets-Sheet 5 +Vds -V'ds 2o 36' l Ids 1 T I'ds Z5" Z5 20 4| 4|36 DRAIN DRAIN M LL GATE SOURCE GATE SOURCE V s I Y 'V'qs 37 i 21' 37'IO 3o 5O 37 LL 3O 55 3 -*-5| 56 g. Vi 2O v0 53-" g l 25 \O l- +V v A 3 17 INVENTOR. v FRANK M.WANLASS BY W/PL% 09M ATTORNEYS Dec. 5, 1967 F. M.WANLASS 3,356,858

LOW STAND-BY POWER COMPLEMENTARY FIELD EFFECT CIRCUITRY Filed June 18,1963 5 Sheets-Sheet 5 V0102 F 1 B 8| W GATE I00 GATE V a 87a 92, I0! 94197 93a SOURCE 87 DRAIN DRAIN SOURCE 9 I P P N I 1 I a alN-TYPEVDS=|OVOLTS I O l l l l -lo a -6 -4 -2 0.5 2 4 6- 6 IO VGSWOLTS) F1g I U0 l l I I I I -2- I Vqsc pTYPE v S VOLTS) INVENTOR.

FRANK M.WANLASS BY I ATTO R N EYS United States Patent C) 3,356,858 LOWSTAND-BY POWER COMPLEMENTARY FIELD EFFECT CIRCUITRY Frank M. Waniass,Mountain View, Calif., assiguor to Fairchild Camera and InstrumentCorporation, Syosset,

N.Y., a corporation of Delaware Filed June 18, 1963, Ser. No. 288,786 3Claims. (307-885) ABSTRACT OF THE DISCLOSURE A combinatorial switchingcircuit using a pair of complementary insulated field-effecttransistors, each having one of its source or drain electrodes connectedto the source or drain electrode of the other; a signal of a singlepredetermined, single polarity voltage is applied to both gates of bothdevices to obtain the necessary switching operation.

The present invention relates in general to transistor circuits, andmore particularly to a circuit employing field-effect semiconductordevices.

Heretofore, logic networks or circuits required passive load elements,such as a resistor or some other passive load component. By employing apassive load element, such as a load resistor, in the logic circuit,power was dissipated during the stand-by period or during the timeintervals in which no switching operation was occurring.

Accordingly, an object of the present invention is to provide circuitsin which power losses are minimized.

Another object of the present invention is to provide logic circuits inwhich power dissipation is reduced during stand-by periods.

Another object of the present invention is to provide a transistorcircuit employing field-efiect semiconductor devices wherein afield-effect semiconductor device of one carrier type is used as theactive load for the field-effect semiconductor device of the oppositecarrier type.

Another object of the present invention is to provide a transistorcircuit in which an inverter action is produced without employing anypassive load element.

Another object of the present invention is to provide a transistorcircuit in which a switching action is created at a faster rate whilereducing the stand-by power normally consumed by the passive loadresistance.

Another object of the present invention is to provide improvedintegrated microcircuits.

Another object of the present invention is to provide switching circuitswherein leakage current is reduced.

Another object of the present invention is to provide logic circuitsadapted for improved fan out.

Another object of the present invention-is to provide logic circuitswith improved tolerance for high temperature differentials betweendifferent circuit elements.

Another object of the present invention is to provide integrated logiccircuits adapted for efficient cooling with a reduced amount of heatexchange area.

Another object of the present invention is to provide micrologiccircuits with a low stand-by power density and a high switching powerdensity, whereby a high packing density is obtained.

Other and further objects and advantages of the present invention willbe apparent to one skilled in the art from the following descriptiontaken in conjunction with the accompanying drawings, in which:

FIG. 1 is an enlarged schematic perspective view of an N-type insulatedgate field-eifect semiconductor device employed in the presentinvention.

FIG. 1A is a vertical sectional view of the N-type insulated gatefield-effect semiconductor device taken along line 1A1A of FIG. 1.

FIG. 2 is an enlarged schematic perspective view of a P-type insulatedgate field-effect semiconductor device employed in the presentinvention.

FIG. 2A is a vertical sectional view of the P-type insulated gatefield-effect semiconductor device taken along line 2A-2A of FIG. 2.

FIG. 3 is a schematic circuit diagram of the N-type insulated gatefield-effect semiconductor device shown in FIG. 1 with the biasingpotential applied thereto.

FIG. 4 is a schematic circuit diagram of the P-type insulated gatefield-effect semiconductor device shown in FIG. 2 with the biasingpotential applied thereto.

FIG. 5 is a schematic diagram of an inverter circuit employing theinsulated gate field-elfect semiconductor devices illustrated in FIGS. 1and 2.

FIGS. 5A and 5B are graphs illustrating input-output characteristics forthe inverter circuit shown in FIG. 5.

FIG. 6 is a schematic diagram of a NAND logic circuit using theinsulated gate field-effect semiconductor devices shown in FIGS. 1 and2.

FIG. 7 is a schematic diagram of a NOR logic circuit employing theinsulated gate field-effect semiconductor devices shown in FIGS. 1 and2.

FIG. 8 is an enlarged schematic cross sectional vieW of the insulatedfield-effect semiconductor device shown in FIGS. 1 and 2 integrated intoa single semiconductor chip or slice.

FIG. 9 is a graph illustrating the drain current as a function of thegate voltage for a typical device shown in FIGS. 1 and 1A.

FIG. 10 is a graph illustrating the drain current as a function of thegate voltage for a typical device shown in FIGS. 2 and 2A.

Illustrated in FIGS. 1 and 1A is an N-type external insulated gatefield-effect semiconductor device 10 employed in the present invention,which comprises a substrate or body 11 of semiconductor material, suchas silicon. The silicon body 11 is doped in a conventional manner withP-type impurities, such as aluminum, gallium, boron or indium. Alsoformed in the silicon body or water 11 are N-type'diffused regions 12and 13, which extend to an upper surface 14 of the P-type silicon wafer11. The N- type diffused regions 12 and 13 are formed in a conventionalmanner by diffusing antimony, arsenic or phosphorus into the siliconbody 11.

An insulated layer 22 preferably of silicon dioxide is thermally grownon the surface 14 of the silicon body 11 and is located in part betweenthe drain contact 20 and the source contact 21. The drain contact 20 andthe source contact 21 are formed by evaporation of a suitable metallicsubstance, such as aluminum; a metallic gate 25 of preferably aluminumis disposed in contact with the portion of the insulated layer 22located between the drain contact 20 and the source contact 21, suchthat the metal overlaps the inside edges of diffused regions 12 and 13.Lead 20 is attached to the drain contact 20* and a lead 25' is attachedto the gate 25. The source electrode 21 has a lead 21' attached theretoand. connected to the substrate 11.

In FIGS. 2 and 2A is illustrated a P-type externally insulated gatefield-eifectsemiconductor device 30 which is also employed in thepresent invention. The P-type insulated field-effect semiconductordevice 30 includes a body or wafer 31 made of suitable semiconductormaterial, such as silicon. The silicon body or substrate 31 is doped ina conventional manner with N-type impurities, such as antimony, arsenicor phosphorous. Also formed in the silicon body 31 are P-type diffusedregions 32 and 33, which extend to an upper surface 35 of the N-typesilicon wafer 31. The P-type diffused regions 32 and 33 are formed in aconventional manner by diffusing a P-type impurity, such as boron orindium into the silicon body 11. An insulated layer 40 preferably ofsilicon dioxide is thermally grown on the surface 35 of the silicon body31 and is located in part between the drain contact 36 and the sourcecontact 37. A suitable metallic substance, such as aluminum, is thenevaporated or otherwise deposited to form the drain contact 36 and thesource contact 37. A metal gate 41 of preferably aluminum i disposed incontact with the portion of the insulated layer 40 located between thedrain contact 36 and the source contact 37, such that the metal overlapsthe inside edges of the diffused regions 32 and 33. Lead 36 is attachedto the drain contact 36 and a lead 41 is attached to the gate 41. Thesource electrode 21 has a lead 21 attached thereto and connected to thesubstrate 31.

In practice, the external insulated gate field-effect semiconductordevices and 30 are produced with relative facility and ease ofoperation. After the silicon substrate or wafer is prepared, it isoxidized by exposure to an oxygen-containing atmosphere at temperaturesin the order of 1200 degrees centigrade. Thereupon, an array of holes isformed in the oxide by photolithographic techniques. Since the remainingoxide film acts as a barrier against the penetration of most donor andacceptor impurities, the contact areas can be diffused selectively intothe holes which have been prepared in the oxide.

A second photoengraving operation is required to reopen the holes overthe diffused regions for electrical contacts, since during the diffusioncycle, oxide is ordinarily regrown. The metal contacts for the source,gate and drain can be applied simultaneously by evaporating a metalfilm, usually aluminum, over the entire surface and removing theunwanted portions by a third photoengraving operation. The source iselectrically connected to the substrate during the preparation of thedevice structure.

As shown in FIG. 3, the N-type external insulated gate field-effectsemiconductor device 10, which is a majority carrier device by electronconduction, has a positive biasing potential Vds applied between thedrain and the source 21 with the drain 20 at a positive voltage and withthe source 21 at ground. When current flows in the semiconductor device10, it flows from the drain 20 to the source 21 through a path disposedtherebetween adjacent the insulated layer 22 and parallel with the uppersurface 14 of the silicon body 11. The path for the current Ids includesthe N-diffused regions 12 and 13 with the portion of the P-type siliconbody 11 therebetween. The flow of current Ids from the drain 20 to thesource 21 is controlled by the potential applied to the gate 25 withrespect to the source 21, which is at ground. In order for current Idsto flow or the device 10 to be rendered conductive, the appliedpotential Vgs between the gate 25 and the source 21 must be equal to orgreater in magnitude than a critical positive potential Vgsc (see FIG.9). When the voltage Vgs falls below the critical positive potential, nocurrent will flow from the drain 20 to the source 21 and the device 10is rendered non-conductive. The critical potential Vgsc required beforethe device 10 first starts to conduct can be regulated by varying thethickness of the insulated layer 22.

The P-type insulated gate field-effect semiconductor device (FIG. 4),which is a majority carrier device by hole conduction, has a negativebiasing potential V'ds applied between the drain 36 and the ource 37with the drain 36 at a negative voltage and with the source 37 atground. When current flows in the semiconductor device 30, it flows fromthe source 37 to the drain 36 through a path disposed therebetweenadjacent the insulated layer 40 and parallel with the upper surface 35of the silicon body 31. The path or channel for the current Ids includesthe P-diffused regions 32 and 33 with the portion of the N-type siliconbody 31 therebetween. The flow of current I'ds from the source 37 to thedrain 36 is controlled by the potential applied to the gate 41 withrespect to the ource 37, which is at ground. In order for current Ids toflow or the device 30 to be rendered conductive, the applied potentialVgs between the gate 41 and the source 37 must be equal to or morenegative in magnitude than a critical negative potential Vgsc (see FIG.10). When the voltage Vgs is less negative than the critical negativepotential, no current will flow from the source, 37 to the drain 36 andthe device 31 is rendered nonconductive. The negative potential Vgscrequired before the device 30 first starts to conduct can be regulatedby varying the thickness of the insulated layer 40.

When an electric field is applied to the surface of an insulatedfieldeffect semiconductor device, the mobile charge carriers within thesemiconductor device are attracted to or repelled from the surface. Inthe event the field so applied is of adeqaute magnitude and of properpolarity, the resulting accumulation of carriers near the surface canresult in the formation of an inversion layer or channel in which themajority carrier near the surface is of opposite type from that in theremainder of the semiconductor body.

By applying to the gate 25 of the N-type field-elfect semiconductordevice 10 (FIGS. 1, 1A and 3) a positive potential relative to thesubstrate 11 equal to or greater than the critical magnitude, an N-typeinversion layer or channel now connects the N-diffused regions 12 and 13for imparting a source-to-drain conduct-ance thereto. In thecomplementary P-type field-effect semiconductor device 30 (FIGS. 2, 2Aand 4), a negative potential is applied to the gate 41 of the criticalmagnitude to form a P-type inversion layer or channel between theP-diffused regions 32 and 33 to impart a drain-to-source conductancethereto. The transistor region between the inversion layer and thesubstrate functions like a P-N junction and remains reverse biased atall times. When the potential applied to a gate is less than thecritical value, the impedance between the source and the drain is veryhigh and corresponding to a reverse biased planar silicon diode.

The voltage applied to the drain of the field-effect semiconductordevices is of a polarity to reverse bias the diffused junction at thedrain contact. Hence, a positive voltage is applied to the drain contactfor diffused N-regions and a negative voltage is applied to the draincontact for diffused P-regions.

According to the present invention, an inverter circuit 50 (FIG. 5)employs the P-type insulated gate field-effect semiconductor device 30and the complementary N-type insulated gate field-effect semiconductordevice 10 to effect a switching operation without employing any passivecomponents, such as a load resistor or some other passive load element.By connecting the sources 36 and 20 of the semiconductor devices 30 and10, respectively, in common over conductors 51 and 52 and by connectingthe gates 41 and 25 of the semiconductor devices 30 and 10,respectively, in common over conductors 53 and 54, the field-effectsemiconductor device '30, a majority hole carrier device, is used as theactive load for the field-effect semiconductor device 10, a majorityelectron carrier device. The converse is also true, since thefield-effect semiconductor device 10, a majority electron carrierdevice, is used as the active load for the field-effect semiconductordevice 30, a majority hole carrier device.

In the operation of the inverter circuit 50, an input signal Vi (FIGS.5, 5A and 5B) is impressed on the gates 25 and 41 of the semiconductordevices it and 30, respectively, through conductors 53-55. An outputsignal V is taken from the drains 20 and 36 of the semiconductor devicesIt and 3!), respectively, over conductors 56, 52 and 51.

When the input signal Vi which is impressed on the gates 25 and 41, isgreater than the positive critical potential, the P-type field-effectsemiconductor device 30 will not conduct and the N-type field-effectsemiconductor device It will conduct making the output voltage V0negative. See FIGS. 5A and SE to show the output voltage V0 for a slowlycharging input signal and for a rapidly rising pulse. When the inputsignal Vi, which is impressed on the gates 25 and 41, is more negativethan the negative critical potential, the N-type field-effectsemiconductor device '10 will not conduct and the P-type fieldefiectsemiconductor device 30 will conduct making the output voltage V0positive.

Accordingly, the circuit 50 produces a switching or invetting actionwithout employing any passive load component, such as a load resistor.Further, it is to be observed from the inverter circuit 50 that only oneof the semiconductor devices and 30 will conduct if the input voltage Viis above a predetermined positive value or below a predeterminednegative value. Therefore, if the total supply voltage difference 2V isgreat enough so that when Vi goes from V to +V, device It will turn onand device 36 will turn off, then power is dissipated only during theswitching operation and not during any stand-by condition. Hence, alow-power system is achieved. In actual practice the power consumedduring a stand-by operation is less than 10 nanowatts per node and, yet,the inverter circuit 56 can effect switching in less than nanoseconds.Moreover, the conducting field-eifect semiconductor device will beturned on to a low resistance state, while the the non-conductingfield-ellect semiconductor device is turned off to an extremely highresistance state, so that output circuit capacities can be rapidlycharged during switching. From the foregoing, it is to be observed thatthe usual requirement of more stand-by power for rapid switching isavoided, since stand-by power is not dissipated in any passive loadresistor or component.

In FIG. 6 is illustrated a NAND logic or gate circuit 60 employing thecomplementary N and P type insulated field-effect semiconductor devices10 and 3! A plurality of P-type insulated field-effect semiconductordevices, such as 30a, 30b and 30c, are connected in parallel. Impressedon the source electrodes 37a, 37b and 37c of the semiconductor devices3ila30c, respectively, is a biasing potential |-V. The output of thelogic circuit is taken at the drain electrodes 36a-3c of thesemiconductor devices 30a-30c, respectively.

Connected in series with the parallel P-type insulated field-effectsemiconductor devices 30a-3ilc are vN-type insulated field-effectsemiconductor devices 1011-100. Applied to the source contact 210 of thesemiconductor device like is a biasing potential -V. The P-typefieldeifect semiconductor device 30a and the N-type field eiIectsemiconductor device 10a are complementary. Further, the P-typefield-effect semiconductor device 3% and the N-type field-efiectsemiconductor device 10b are complementary. Similarly, the P-typefield-effect semiconductor device 300 and the N-type field-efiectsemiconductor device ltic are complementary.

In the operation of the NAND logic circuit 60, an input signal of +V orV is impressed on the gates a and 41a of the complementary semiconductordevices 10a and a. In a similar manner, an input signal B is fed to thegates 25]) and 41b of the complementary semiconductor devices 1% and30b. Likewise, an input signal C is transmitted to the gates of thecomplementary semiconductor devices 100 and Site. The input signals A, Band C are transmitted simultaneously to the field-efiect semiconductordevices in the manner above indicated.

Should all signals A, B and C be at +V so that their associated P-typefield-effect semiconductor devices are 6 not conductive and theirassociated N-type devices are conductive, then there will be a negativeoutput voltage at Y. When the semiconductor devices 30a30c conduct, thecomplementary semiconductor devices 1i)a1(lc, respectively, provide ahigh impedance and the active load.

A NOR logic or gate circuit 70 is shown in FIG. 7, which employs thecomplementary N and P type insulated field-eifect semiconductor devices16 and 30. A plurality of N-type insulated field-effect semiconductordevices, such as 10d-10f, are connected in parallel. Impressed on thesource electrodes 2103-21) of the semiconductor devices 10d-10f is abiasing potential -V. Connected in series with the semiconductor devices10d-10f are parallel connected P-type insulated fieldetfectsemiconductor devices 301L301. Applied to the source electrode 37 of thesemiconductor device 30f is a biasing potential V. The output of thelogic circuit 70 is taken at Y at the drain electrodes 20d2tlf of thesemiconductor devices 10d-10f.

The N-type field-effect semiconductor device 10d and the P-typefield-effect semiconductor device 30d are complementary. Likewise, theN-type field-effect semiconductor device 10c and the P-type field-eifectsemiconductor device 30c are complementary. Similarly, the N- typefield-effect semiconductor device 10 and the P-type field-effectsemiconductor device 30f are complementary.

In the operation of the NOR logic circuit 70, an input signal D istransmitted to the gates 25d and 41d of the complementary semiconductordevices 10d and 30d. Likewise, an input signal E is fed to the gates 252and 41e of the complementary semiconductor devices lile and 30a. In asimilar manner, an input signal F is impressed on the gates 25 and 41 ofthe complementary semiconductor devices 10f and 30 If any one or more ofthe input signals D, E and F is equal to +V, then the associated P-typefield-effect semiconductor device or devices 30(1-38 will not conductand its or their complementary N-type field-effect semiconductor devices104-101 will conduct. As a result thereof, a negative potential willappear at the terminal Y. The non-conducting field-effect semiconductordevice or devices 10d-10f provide a high impedance and also provide theactive load, respectively, for the complementary conducting field-effectsemiconductor devices 30d- 30 Hence, if any one or more of the P-typesemiconductor devices 30d-30f conducts, a positive output signal isproduced at terminal Y.

Illustrated in FIG. 8 is a semiconductor unitary structure 80, whichcomprises a plurality of semiconductor devices, such as N-type externalinsulated gate field-eifect semiconductor device 81 and a complementaryP-type insulated gate field-eifect semiconductor device 82, which areintegrally formed on a single chip or slice 83.

In the preferred embodiment the chip or body 83 is of silicon and isdoped in a conventional manner with N-type impurities, such as antimony,arsenic or phosphorous. For producing the P-type field-effectsemiconductor device 82, P-type diffused regions 84 and 85 are formed inthe N-type silicon body 83 and extend to an upper surface 86 of thesilicon chip 83. The P-type diffused regions 84 and 85 are formed in aconventional manner by diffusing a P-type impurity such as aluminum,boron or indium into the silicon body 83.

For producing the N-type field-eifect semiconductor device 81, thesilicon body 83 is doped in a conventional manner with P-typeimpurities, such as aluminum, boron or indium to form a P-type region 90within the N-type silicon body 83. Formed in the P-type region 90 are N-type difiused regions 91 and 92, which extend to the upper surface 86 ofthe silicon body 83.

The N-type difiused regions 91 and 92 are formed in a conventionalmanner by difiusing antimony, arsenic or phosphorous into the P-typeregion 90. An insulated layer 95 preferably of silicon dioxide isthermally grown on the surface 86 of the silicon body 83 and is locatedin part between associated drain and source contacts. The drain contacts87 and 93, as well as the source contacts 88 and 94, are metallized witha suitable metallic substance, such as aluminum. Source contact 93 alsoserves as the metal interconnection between P-type region 90 and N-typeregion 92.

A metallic gate 96 of preferably aluminum for the P- type field-effectsemiconductor device 82 is disposed in contact with the portion of theinsulated layer 95 located between the drain 87 and the gate 88.Similarly, a me tallic gate 97 of preferably aluminum for the N-typefieldeffect semiconductor device 81 is disposed in contact with theportions of the insulated layer 95 located between the drain 93 and thesource 94.

The P-type insulated gate field-effect semiconductor device 82 operatesand functions in the manner previously described in detail for theP-type insulated gate field-effect semiconductor device 30. Likewise,the N-type external insulated gate field-effect semiconductor device 81opcrates and functions in the manner previously described in detail forthe N-type external insulated gate field-effect semiconductor device 10.

A lead 87a is attached to the source electrode 87 of the semiconductordevice 82 and is connected to a source of electrical energy. Throughthis arrangement, a +V biasing potential is applied to the sourceelectrode 87. In a like manner, a lead 93a is connected to the sourceelectrode 93 of the semiconductor device 81 and is connected to thesource of electrical energy. Through this arrangement, a V biasingpotential is impressed on the drain electrode 93. It is to be noted thatall junctions will be either at zero bias or at reverse bias, but itwill never be at forward bias. The gates 96 and 97 of the semiconductordevices 82 and 81, respectively, are connected in common over aconductor 100. Fed to the conductor 100 is an input signal Vi. A commonconducting strip 101 is attached to the source electrodes 88 and 94 ofthe semiconducting devices 82 and 81, respectively. A lead 102 isconnected to the conducting strip 101 for transmitting the output signaltherefrom.

From the foregoing, it is observed that an inverter circuit 81a isformed from the semiconductor unitary structure 80. The operation of theinverter or switching circuit 81a will now be described. When the inputsignal Vi, which is impressed on the gates 96 and 97, is equal to orgreater than the positive critical potential, the P-type fieldeffectsemiconductor device 82 will not conduct and the N-type field-effectsemiconductor device 81 will conduct. The output voltage V is,therefore, negative.

When the input signal Vi, which is impressed on the gates 96 and 97, isequal to or more negative than the critical potential, the N-typefield-effect semiconductor device 81 will not conduct and the P-typefield-effect semiconductor device 82 will conduct. The output voltage V0is positive.

Therefore, the circuit 81a produces a switching or inverting actionwithout employing any passive load com ponent, such as a load resistor.Further, the field-effect semiconductor device 82, a majority holecarrier device, is employed as the active load for the field-effectsemiconductor device 81, a majority electron carrier device. Theconverse is also true, since the field-effect semiconductor device 82, amajority electron carrier device, is used as the active load for thefield-effect semiconductor device 81, a majority hole carrier device.

The complementary N and P type insulated gate fieldetfect semiconductordevices are employed by the circuits of the present invention to producelow stand-by power systems. Through the exclusive use of these devices,the high speed switching circuits of the present invention dissipateappreciable power only during the switching transient. Theabove-described circuits of the present invention are relativelyunaffected in performance by ambient tempcratures up to approximately150 degrees centigrade,

8 since they employ only majority carrier devices which are relativelytemperattire-independent. Systems employing the circuits of the presentinvention perform in spite of large temperature gradients within thesystem.

Because of the voltage-controlled nature of the active elements, thereare no problems of unequal sharing by the next logic stage, at least atlow speeds. Thus, the fan out capabilities are extremely favorable.Further, the circuits of the present invention offer large voltageswings and low dynamic impedance in both states. This is desirable forimmunity against noise pulses.

It is to be understood that modifications and variations of theembodiments of the invention disclosed herein may be resorted to withoutdeparting from the spirit of the invention and the scope of the appendedclaims.

Having thus described my invention, what I claim and desire to protectby Letters Patent is:

1. A combinational switching circuit comprising a first semiconductorbody of one conductivity type with a plurality of spaced diffusedregions of a conductivity type opposite to said body and forming PNjunctions therewith extending to a surface of said body, a first pair ofsource and drain electrodes on said body adjacent two of said diffusedregions at said surface, a first insulating layer on said surface ofsaid body between said drain and source electrodes, a first gateelectrode adjacent said first insulating layer, a pair of spaceddiffused regions of said one conductivity type formed within a third oneof said plurality of spaced diffused regions and forming PN junctionswith said third diffused region extending to said surface, a second pairof source and drain electrodes on said pair of spaced diffused regions,a second insulating layer on the surface of said third difiused regionbetween said second pair of source and drain electrodes, a second gateelectrode on said second insulating layer, means for applying biasingpotentials of the same polarity to both of said gate electrodes.

2. A circuit comprising a first insulated gate field-effect transistorhaving a substrate of one conductivity type, an insulating layeradjacent said substrate, a metal layer upon said insulating layeropposite said substrate, and a channel region adjacent said insulatinglayer having a conductivity type opposite said substrate uponapplication of a first predetermined bias voltage to said metal layer,thereby forming a PN junction between said substrate and said channelregion, source and drain electrodes on opposite ends of said channelregion, a second insulated gate fieldeffect transistor having asubstrate of said opposite conductivity type, an insulating layeradjacent said substrate, a metal layer upon said insulating layeropposite said substrate, and a channel region adjacent said insulatinglayer having said one conductivity type upon application of a secondpredetermined bias voltage to said metal layer of polarity opposite tosaid first predetermined bias voltage, source and drain electrodes onopposite ends of said channel region, one of said source and drainelectrodes of said first insulated gate field-effect transistor beingcoupled to one of said source and drain electrodes of said secondinsulated field-effect transistor, a means for applying a fixed biasvoltage across the other of said source and drain electrodes of saidfirst and second insulated field-effect transistors, and a means forapplying a voltage signal of a single predetermined polarity to both ofsaid metal layers of said first and second insulated gate field-effecttransistors adapted to render said first insulated gate field-effecttransistor conductive between its source and drain electrodes whilerendering said second insulated gate fieldetfect transistornon-conductive between its source and drain electrodes, whereby saidsecond non-conductive insulated gate field-effect transistor is employedas the active load for said first conductive insulated gate field-effecttransistor.

3. The circuit of claim 2 further characterized by the channel region ofeach insulated gate field effect device being of the same conductivitytype as the substrate of said insulated gate field effect device whenthere is no 10 bias voltage applied to the metal layer of said insulated3,215,861 11/1965 Sekely 307-885 gate field effect device. 3,222,61012/1965 Evans et a1 33038 References Cited OTHER REFERENCES UNITEDSTATES PATENTS 5 REC Tech. Notes, No.1654, November 1965.

3,135,926 6/1964 Bockemuehl JAMES D. KALLAM, Primary Examiner. 3,201,5748/1965 Szekely. 3,213,299 10/1965 Rogers 307-885 JOHN HUCKERT Exammer-3,215,859 11/ 1965 Sorchych 307-885 R. SANDLER, Assistant Examiner.

2. A CIRCUIT COMPRISING A FIRST INSULATED GATE FIELD-EFFECT TRANSISTORHAVING A SUBSTRATE OF ONE CONDUCTIVITY TYPE, AN INSULATING LAYERADJACENT SAID SUBSTRATE, A METAL LAYER UPON SAID INSULATING LAYEROPPOSITE SAID SUBSTRATE, AND A CHANNEL REGION ADJACENT SAID INSULATINGLAYER HAVING A CONDUCTIVITY TYPE OPPOSITE SAID SUBSTRATE UPONAPPLICATION OF A FIRST PREDETERMINED BIAS VOLTAGE TO SAID METAL LAYER,THEREBY FORMING A PN JUNCTION BETWEEN SAID SUBSTRATE AND SAID CHANNELREGION, SOURCE AND DRAIN ELECTRODES ON OPPOSITE ENDS OF SAID CHANNELREGION, A SECOND INSULATED GATE FIELDEFFECT TRANSISTOR HAVING ASUBSTRATE OF SAID OPPOSITE CONDUCTIVITY TYPE, AN INSULATING LAYERADJACENT SAID SUBSTRATE, A METAL LAYER UPON SAID INSULATING LAYEROPPOSITE SAID SUBSTRATE, AND A CHANNEL REGION ADJACENT SAID INSULATINGLAYER HAVING SAID ONE CONDUCTIVITY TYPE UPON APPLICATION OF A SECONDPREDETERMINED BIAS VOLTAGE TO SAID METAL LAYER OF POLARITY OPPOSITE TOSAID FIRST PREDETERMINED BIAS VOLTAGE, SOURCE AND DRAIN ELECTRODES ONOPPOSITE ENDS OF SAID CHANNEL REGION, ONE OF SAID SOURCE AND DRAINELECTRODES OF SAID FIRST INSULATED GATE FIELD-EFFECT TRANSISTOR BEINGCOUPLED TO ONE OF SAID SOURCE AND DRAIN ELECTRODES OF SAID SECONDINSULATED FIELD-EFFECT TRANSISTOR, A MEANS FOR APPLYING A FIXED BIASVOLTAGE ACROSS THE OTHER OF SAID SOURCE AND DRAIN ELECTRODES OF SAIDFIRST AND SECOND INSULATED FIELD-EFFECT TRANSISTORS, AND A MEANS FORAPPLYING A VOLTAGE SIGNAL OF A SINGLE PREDETERMINED POLARITY TO BOTH OFSAID METAL LAYERS OF SAID FIRST AND SECOND INSULATED GATE FIELD-EFFECTTRANSISTORS ADAPTED TO RENDER SAID FIRST INSULATED GATE FIELD-EFFECTTRANSSISTOR CONDUCTIVE BETWEEN ITS SOURCE AND DRAIN ELECTRODES WHILERENDERING SAID SECOND INSULATED GATE FIELD-EFFECT TRANSISTORNON-CONDUCTIVE BETWEEN ITS SOURCE AND DRAIN ELECTRODES, WHEREBY SAIDSECOND NON-CONDUCTIVE INSULATED GATE FIELD-EFFECT TRANSISTOR IS EMPLOYEDAS THE ACTIVE LOAD FOR SAID FIRST CONDUCTIVE INSULATED GATE FIELD-EFFECTTRANSISTOR.